What RFIC interviewers are evaluating
An RFIC interview may begin with a TX or RX specification, a link budget, or a transistor-level LNA, mixer, or oscillator. In every case, the interviewer is testing whether you can connect a block-level circuit to a measurable system-level specification.
A strong candidate identifies the dominant mechanism, chooses an approximation that fits the question, and explains the tradeoffs between gain, bandwidth, noise, linearity, power, and area.
A useful preparation rule: for every RF equation, know the block-level meaning, the transistor-level mechanism, and the limiting case where the approximation stops working.
RFIC interview topic checklist
Architecture and system budgets
RX and TX chains, cascaded gain, noise figure, compression, dynamic range, sensitivity, and blocker requirements.
Noise and linearity
Channel thermal noise, flicker noise, noise factor, IIP2, IIP3, P1dB, intermodulation, desensitization, and tradeoffs with power and gain.
Matching and gain
Impedance transformation, S-parameters, stability, available and transducer gain, broadband versus narrowband design, and passive loss.
Core RF blocks
LNAs, mixers, I/Q paths, image rejection, oscillators, phase noise, frequency dividers, and PLLs.
Common RFIC question styles
- TX and RX system budget: calculate cascaded noise figure, gain, linearity, sensitivity, and EVM, then identify the dominant factor in the chain.
- LNA design: compare common-source and common-gate approaches; analyze source degeneration; calculate impedance and noise matching; and evaluate noise, gain, and stability.
- Mixer design: identify the desired signal and image, conversion gain or loss, port feedthrough, linearity, switching nonidealities, and flicker noise.
- I/Q and image rejection: track complex frequency translation, amplitude/phase mismatch, and sideband rejection.
- Oscillators: explain startup condition, negative resistance, tank loss, amplitude limiting, tuning range, and phase noise.
- PLLs: analyze how loop bandwidth and loop-filter order affect reference noise, VCO noise, settling time, stability, and spurs; include the effect of division ratio.
- Power amplifiers (PAs): calculate efficiency; analyze the tradeoff between maximum output power and efficiency; evaluate the tradeoff between efficiency and linearity; and assess stability.
A systems-to-circuits method for RFIC questions
- Translate the specification. Write the relevant input/output quantity, units, bandwidth, impedance, and reference plane.
- Place the question in the chain. Identify what comes before and after the block so loading and cascade effects are not missed.
- Identify the dominant factor. Determine which mechanism primarily controls the requested specification—for example, a noise source, passive loss, switching nonideality, feedback, or tank Q.
- Choose the simplest valid model. Use a system budget, small-signal model, time-varying model, or complex-signal view intentionally rather than mixing them up.
- State the tradeoff. Explain what improves, what degrades, and what resource—power, voltage headroom, area, calibration, or time—pays for it.
- Check physical limits. Verify units, passive-loss penalties, available headroom, stability, and whether the result is plausible for the stated frequency and technology.
RFIC preparation mistakes that create weak answers
- Applying RF equations without first defining the quantity and stating the assumptions—for example, cascaded noise figure, IIP3 versus OIP3, or phase noise at a stated offset frequency.
- Confusing power gain, voltage gain, available gain, and transducer gain.
- Losing the desired or image sign during complex frequency translation.
- Ignoring passive loss before the first gain stage or missing its impact on noise.
- Discussing matching without checking stability, noise, bandwidth, and the impedance presented by the source and load stages.
- Optimizing a transistor-level metric without considering its impact on the RX or TX chain.
Practice the transitions between topics
Uplevel combines circuit foundations, analog design, and RFIC systems and blocks in one question-driven program. The free diagnostic evaluates different layers so you can see whether your reasoning survives time pressure.
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